1. Field of the Invention
The present invention relates to communication receivers and more particularly to a data limiter circuit having a variable time constant for converting an analog signal to a digital signal.
2. Background of the Invention
Communications systems in general and paging systems in particular using selective call signalling have attained widespread use for calling a selected paging system receiver by transmitting information from a base station transmitter to the paging receiver. Modern paging receivers have achieved multifunction capability through the use of microprocessors which allow the paging receiver to respond to information having various combinations of tone, tone and voice, or data messages. This information is transmitted using any number of paging coding schemes and message formats.
A block diagram of a prior art receiving system suitable for use in a synchronous paging system is illustrated in FIG. 1. The receiver comprises an antenna 10 which receives an RF signal and transmits it to a receiver 12 where the RF signal is amplified and converted into a first intermediate frequency (I.F.) signal by an RF amplifier and first mixer, respectively. This I.F. signal is preferably directed to the receiver's backend where a first I.F. signal is converted to a second I.F. signal, in a dual conversion receiver, amplified, limited, demodulated, and filtered. The voltage level of the output signal at output 14 represents coded binary data or digital data. The output 14 of the receiver 12 is capacitively coupled to the input 15 of a data limiter 16 by way of a coupling capacitor 18 and bias resistor 17 connected between the differential inputs of the data limiter 16. The output 13 of the data limiter 16 is directed to a data processor 20 for further desired processing.
The receiver system also includes one or more switches (normally transistors) connected between the various components of the receiver system and the power supply (B+). A switch 22 is periodically turned on and off under control of processor 20 by a battery saver routine 24 to provide a battery saving feature, which is a technique well known to those skilled in the art. A switch 26 (such as a transistor) is periodically closed to precharge the coupling capacitor 18, preferably by placing a resistor 27 in parallel with the limiter bias resistor 17 and input impedance, thereby reducing the overall RC time constant. Switch 26 is normally closed simultaneously with switch 22, but normally remains closed for a shorter time than switch 22 to provide this precharging.
Normally, in situations where it is necessary to pass digital data from the receiver 12 to the data limiter 16, capacitor 18 will be a relatively large value in order to pass low frequency information and digital signals. Thus, a long time may be required to charge the capacitor 18, especially when it is connected to a high impedance such as the limiter bias resistor 17 for the data limiter 16. A long charge time necessitates the receiver "on" time being increased correspondingly to insure that capacitor 18 is charged to its correct bias point and that valid data is delivered to the data processor during the data decoding interval. The battery saver feature is clearly degraded by the extended receiver on time since this consumes more battery energy than is desirable. Switch 26 is used to alleviate this situation by providing a momentary low impedance charge path in parallel with the data limiter bias resistor 17 immediately upon receipt of power from the battery saver 24, that is, when the switch 22 is closed. This allows capacitor 18 to more rapidly charge to the bias voltage, depending upon the average value of the incoming data. If the incoming data can be depended upon to have no long strings of 1's or 0's, the charging of capacitor 18 will closely approximate the desired bias voltage. Data decoding of the received bit stream can begin more rapidly and continue until the battery voltage B+ is again removed by switch 22, thereby enhancing the battery saving feature.
However, several problems exist in using a coupling capacitor 18. Referring briefly to FIG. 2, there is shown, along with the battery saver strobe signal A, an input signal H, a threshold voltage G, and an output signal E of the prior art data limiter 16. The input signal H includes digital data modulated on the waveform. When signal H passes through threshold signal G (time t2), data is detected and decoded as is illustrated in signal E. Note that even with precharging, data before time t2 is lost. Under ideal conditions (an alternating 1-0 data pattern), the average voltage level at the output of the receiver will be at the desired carrier reference voltage, that is, the voltage level which corresponds to an undeviated RF signal. During the precharge interval, capacitor 18 will charge to a bias voltage which is consistent with this carrier reference voltage and proper data decoding will occur. If a long string of 1's or 0's is received immediately before the opening of switch 26, the average DC voltage of the receiver output 14 will be offset from the desired reference. The average DC voltage is increased if a large number of 1's are received or decreased if a large number of 0's are received.
Thus, relatively substantial DC voltage offsets from the correct bias voltage across capacitor 18 may still occur if this technique is used in an asynchronous system with unpredictable data patterns. This may result in erroneous outputs from the data limiter, long response time (the delay required between receipt of a signal and occurrence of valid data at the limiter output), and may ultimately result in the end user receiving no message or an erroneous message which differs from the originally transmitted message.